1. Field of the Invention
The present invention relates to an interface system among integrated circuits (hereinafter referred to as ICs). More particularly, this invention relates to an interface system and method thereof which requires only one signal line interconnecting the ICs, thereby simplifying the interconnection of the ICs.
2. Discussion of Related Art
Conventionally, there are two methods for a serial interface among ICs: a three-line type serial interface method which uses three bus lines for an interface among ICs; and a two-line type serial interface method using two bus lines.
FIG. 1 is a block diagram of a conventional three-line type serial interface method.
FIG. 2 is a block diagram of a conventional two-line type serial interface method.
Referring to FIG. 1, the three-line type serial interface method shows three bus lines between a master chip A and a low order chip B cascaded to the master chip A. Each integrated circuit (IC) (or chip) has an output terminal S.sub.OUT for outputting data, an input terminal S.sub.IN for inputting data where the S.sub.OUT of one IC is connected to the S.sub.IN of another IC, and a clock line S.sub.CLK for adjusting a synchronization to achieve serial communication.
The three-line type serial interface method adjusts synchronization to a clock signal outputted from the master IC A, and transmits data outputted from an output terminal S.sub.OUT of the master IC A to an input terminal S.sub.IN of the low order IC B, thereby achieving an interface between the two ICs.
Accordingly, a data transmission/reception operation between the master IC and the low order IC progresses simultaneously using three signal lines.
As shown in FIG. 2, a plurality of ICs (A, B, C, . . .) are connected to two bus lines in the two-line type serial interface method. In the two-line type serial interface method, data of each IC are outputted by adjusting synchronization to a clock signal CLK outputted from a master IC.
The conventional serial interface systems have a problem, namely that they require a plurality of signal lines in order to communicate among the plurality of ICs.